- Source: Control store
A control store is the part of a CPU's control unit that stores the CPU's microprogram. It is usually accessed by a microsequencer. A control store implementation whose contents are unalterable is known as a Read Only Memory (ROM) or Read Only Storage (ROS); one whose contents are alterable is known as a Writable Control Store (WCS).
Implementation
= Early use
=Early control stores were implemented as a diode-array accessed via address decoders, a form of read-only memory. This tradition dates back to the program timing matrix on the MIT Whirlwind, first described in 1947. Modern VLSI processors instead use matrices of field-effect transistors to build the ROM and/or PLA structures used to control the processor as well as its internal sequencer in a microcoded implementation. IBM System/360 used a variety of techniques: CCROS (Card Capacitor Read-Only Storage) on the Model 30, TROS (Transformer Read-Only Storage) on the Model 40, and BCROS (Balanced Capacitor Read-Only Storage) on Models 50, 65 and 67.
= Writable stores
=Some computers are built using "writable microcode" — rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a writable control store or WCS. Such a computer is sometimes called a Writable Instruction Set Computer or WISC. Many of these machines were experimental laboratory prototypes, such as the WISC CPU/16 and the RTX 32P.
The original System/360 models have read-only control store, but later System/360, System/370 and successor models load part or all of their microprograms from floppy disks or other DASD into a writable control store consisting of ultra-high speed random-access read–write memory. The System/370 architecture includes a facility called Initial-Microprogram Load (IML or IMPL) that can be invoked from the console, as part of Power On Reset (POR) or from another processor in a tightly coupled multiprocessor complex. This permitted IBM to easily repair microprogramming defects in the field. Even when the majority of the control store is stored in ROM, computer vendors would often sell writable control store as an option, allowing the customers to customize the machine's microprogram. Other vendors, e.g., IBM, use the WCS to run microcode for emulator features and hardware diagnostics.
Other commercial machines that use writable microcode include the Burroughs Small Systems (1970s and 1980s), the Xerox processors in their Lisp machines and Xerox Star workstations, the DEC VAX 8800 ("Nautilus") family, and the Symbolics L- and G-machines (1980s). Some DEC PDP-10 machines store their microcode in SRAM chips (about 80 bits wide x 2 Kwords), which is typically loaded on power-on through some other front-end CPU. Many more machines offer user-programmable writable control stores as an option (including the HP 2100, DEC PDP-11/60 and Varian Data Machines V-70 series minicomputers).
The Mentec M11 and Mentec M1 store its microcode in SRAM chips, loaded on power-on through another CPU.
The Data General Eclipse MV/8000 ("Eagle") has a SRAM writable control store, loaded on power-on through another CPU.
WCS offers several advantages including the ease of patching the microprogram and, for certain hardware generations, faster access than ROMs could provide. User-programmable WCS allow the user to optimize the machine for specific purposes. However, it also had the disadvantage of making it harder to debug programs, and making it possible for malicious users to negatively affect the system and data.
Some CPU designs compile the instruction set to a writable RAM or FLASH inside the CPU (such as the Rekursiv processor and the Imsys Cjip), or an FPGA (reconfigurable computing).
Several Intel CPUs in the x86 architecture family have writable microcode, starting with the Pentium Pro in 1995.
This has allowed bugs in the Intel Core 2 microcode and Intel Xeon microcode to be fixed in software, rather than requiring the entire chip to be replaced.
Such fixes can be installed by Linux, FreeBSD, Microsoft Windows, or the motherboard BIOS.
= Timing, latching and avoiding a race condition
=The control store usually has a register on its outputs. The outputs that go back into the sequencer to determine the next address have to go through some sort of register to prevent the creation of a race condition.
In most designs all of the other bits also go through a register. This is because the machine will work faster if the execution of the next microinstruction is delayed by one cycle. This register is known as a pipeline register. Very often the execution of the next microinstruction is dependent on the result of the current microinstruction, which will not be stable until the end of the current microcycle. It can be seen that either way, all of the outputs of the control store go into one big register. Historically it used to be possible to buy EPROMs with these register bits on the same chip.
The clock signal determining the clock rate, which is the cycle time of the system, primarily clocks this register.
References
Further reading
Everett, Robert Rivers; Swain, F. E. (1947-09-04). Whirlwind I Computer Block Diagrams (PDF). Project Whirlwind (Device 24-X-3). Vol. 1. Cambridge, Massachusetts, USA: Servomechanisms Laboratory Massachusetts Institute of Technology. Project DIC 6345, Report R-127. Archived (PDF) from the original on 2021-08-15. Retrieved 2021-11-12. (132 pages)
Everett, Robert Rivers; Swain, F. E. (1947-09-04). Whirlwind I Computer Block Diagrams (PDF). Project Whirlwind (Device 24-X-3). Vol. 2. Cambridge, Massachusetts, USA: Servomechanisms Laboratory Massachusetts Institute of Technology. Project DIC 6345, Report R-127. Archived (PDF) from the original on 2021-08-15. Retrieved 2021-11-12. (79 pages)
Smith, Richard E. (October–December 1988). "A Historical Overview of Computer Architecture". Annals of the History of Computing. 10 (4). IEEE: 277–303. doi:10.1109/MAHC.1988.10039. S2CID 16405547. Retrieved 2006-06-21.
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