• Source: Fujitsu VP

The Fujitsu FACOM VP is a series of vector supercomputers designed, manufactured, and marketed by Fujitsu. Announced in July 1982, the FACOM VP were the first of the three initial Japanese commercial supercomputers, followed by the Hitachi HITAC S-810 in August 1982 and the NEC SX-2 in April 1983.




Context in the supercomputer market


The FACOM VP were sold until they were replaced by the VP2000 family in 1990. Developed with funding from the Ministry of International Trade and Industry, the FACOM VP was part of an effort designed to wrest control of the supercomputer market from the collection of small US-based companies like Cray Research. The FACOM VP was marketed in Japan by Fujitsu, where the majority of installations were located. Amdahl marketed the systems in the US and Siemens in Europe. The ending of the Cold War during this period made the market for supercomputers dry up almost overnight, and the Japanese firms decided that their mass-production capabilities were better spent elsewhere.




Development


Fujitsu had built a prototype vector co-processor known as the F230-75, which was installed attached to their own mainframe machines in the Japanese Atomic Energy Commission and National Aerospace Laboratory in 1977. The processor was similar in most ways to the famed Cray-1, but did not have vector chaining capabilities and was therefore somewhat slower. Nevertheless, the machines were rather inexpensive, and during the late 1970s supercomputers were seen as a source of national pride, and an effort started to commercialize the design by combining it with a scalar processor to create an all-in-one design.
The result was the VP-100 and VP-200, announced in July 1982. These two models differed primarily in clock rates. Lower-end models were spun off as the VP-30 and VP-50. In 1986 a two-pipeline version was released as the VP-400. The next year the entire series was updated with the addition of a new vector unit that supported a multiply-and-add unit that could retire two results per clock cycle. This resulted in the "E series", VP-30E through VP-400E.




Issues with the design


One problem with the design was the limited memory bandwidth as a result of having only one load-store unit. Even on the top-end VP-400E it could drive only 4.57 GB/s peak, limiting the maximum performance to only 0.5 GFLOPS for 64-bit operands. US designs focused on this problem in the early 1980s, and the contemporary Cray-2 could drive about 2 GB/s per processor, with up to four processors.




References



R.W. Hockney; C.R. Jesshope (1988). Parallel Computers 2: Architecture, Programming and Algorithms. CRC Press. pp. 191–196.

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